Agentic AI 时代 AMD EPYC 9006 CPU 的定位与应用展望

AMD AAI Venice SP7 开盖展示

我想静下心来，从 Agentic AI 时代的角度，讨论下一代 AMD EPYC “Venice” CPU。我们此前已在 Substack 上持续报道这个话题，并且上周发布了一篇关于 AMD EPYC 9006 Venice 的深度文章。不过，我希望将这一视角进一步应用到下一代 AMD EPYC CPU，因为我认为 AMD 的服务器 CPU 战略正在变得更加广泛。

AMD EPYC 9006 CPU 与 Agentic AI：一种视角

几周前，在上述 Substack 文章中，我们探讨了在 Agentic AI 时代，成为一颗数据中心 CPU 究竟意味着什么，因为数据中心运行着大量处理器。这里不再展开细节，但可以想象：一颗功耗 500W、拥有三位数核心数量、连接海量 PCIe 和内存资源的 CPU；以及一颗功耗不足 6W、性能较低、采用双四核 Arm 架构、可能只配备 2GB 或 4GB 内存的处理器。你完全可以认为，数据中心里存在许多不同类型的处理器。

我们多年来一直在 STH 强调这一点：多数服务器中的 ASPEED BMC 运行自身固件，拥有独立的内存、存储和网络连接，运行自己的 Web 服务器与 API 等，并且位于服务器内部。如果将它称作数据中心 CPU，那么，同样的处理器若部署在后门热交换器中、用于监控温度、泵和流量，是否也算数据中心 CPU？位于电源架中的处理器又是否算？这份名单可以无限延伸。因此，我们必须界定一个更具相关性的处理器范围，以下便是我们得出的框架。

Axautik Group 数据中心 CPU 测试 2026-Q3

在此基础上，我们识别出这些场所中常见的节点类型。我们收到了关于 Substack 框架的一些反馈，因此为读者提供一个更为扩展的视图以供参考：

Axautik Group 服务器 CPU 映射框架 2026-Q3

如今这个话题规模如此庞大，我希望将 Venice 放入上述部分领域中进行定位。销售 CPU 的厂商经常宣称自家芯片最适合“一切”工作负载，但这种“一切”通常是在特定赛道内。AMD 自身的产品阵容同样体现了这一点，因为 EPYC 9006 家族拥有许多不同版本。

首先是 AMD EPYC SP7。在前几代产品中，这一配置属于旗舰或“高端”配置。如今，它只是众多可被视为旗舰的平台之一。关键规格包括：最高 256 核、512 线程，适用于一款 600W 产品；或最高 96 核、192 线程、频率最高 5GHz，适用于一款 500W 产品。尽管该系列存在一款 64 核 300W 产品，但已公开的九款 SKU 中，有五款功耗为 500W，另有两款达到 600W。其 1.6TB/s 内存带宽，似乎对应 16 个通道的 12800MT/s MRDIMM。

AMD AAI EPYC 9006 SP7

Venice 的另一端则是 SP8 插槽版本，其配置范围从 130W 至 400W、8 核至 128 核。

AMD AAI EPYC 9006 SP8

如果将其映射到 Intel Xeon，可以将其理解为类似 Intel Xeon 6700P 与 Xeon 6900P 系列的关系，只是采用了更新的核心、更新的内存标准、PCIe 标准等。当市场上存在一款 256 核/512 线程、拥有更高内存带宽和 I/O 能力的产品时，我不确定 288 核 Xeon 6900E 系列会处于怎样的竞争位置。之所以提及 Intel Xeon 6 的对比，是因为 Intel 的产品规划数年前就预见到，需要将市场拆分为高端插槽和较低端插槽。AMD 如今也在采取类似做法。

我认为这是一个关键点，特别是在所有人都希望拥有一颗面向 Agentic AI 的 CPU 之际。一部分工作负载位于 AI Factory 中，但大量负载同样会落在其他数据中心。使用更大的插槽来追求最高性能与密度，同时采用更小的插槽以适配更传统的机架，似乎是正确方向。

接下来是一款应当让业界感到兴奋的芯片。EPYC 9006X 配备 1.1GB L3 缓存，即每核心 12MB L3 缓存，同时具备 1.6TB/s 内存带宽和更高频率；它同样是一颗 SP7 CPU，但面向更多 HPC 应用。它接替了 2022 年的 AMD Milan-X 和 2023 年的 AMD Genoa-X, 并带来更现代的核心以及其他各方面的更新。

AMD AAI EPYC 9006X SP7 Venice X

有意思的是，EPYC 9006X 将稍晚推出，但它理应会是一头性能怪兽。换一种说法：业界有许多人观察 Meta Muse 及其 2 vCPU 环境——即一个启用 SMT=2 的核心——并认为目标是尽可能在一个插槽中塞入更多 vCPU。另一些人则认为，正确形态应是每插槽不足 100 个核心，同时最大化内存带宽和单核性能。EPYC 9006X 正是后者在理想世界中想要的产品。

随后是 AI 主机处理器 AMD EPYC 9006 LP，它将 LPDDR5X 引入 AMD EPYC 产品线。在我们看来，这是一款直接与 NVIDIA Grace 或 Vera CPU 竞争的产品，旨在进入 Helios Rack。

AMD AAI EPYC 9006 LP Verano

过去一年左右，我们已经见到多款搭载 192 核 Turin Dense 处理器的 8×GPU AMD Instinct 服务器。我们测试的其他系统则配备 64 核或 128 核 Turin 处理器。对于这些机架级设计而言，答案似乎是在牺牲机架内最高核心数量的前提下，满足既定的功耗范围。从技术上说，这是一颗 Verano 而非 Venice CPU，因此我们将本文标题从 Venice EPYC 9006 作了调整，以便更轻松地将该系列纳入数据中心 CPU 框架。

在完成上述概览后，是时候进行映射了。我们拥有多款 EPYC 9006 系列处理器和一张图表，因此现在该开始映射。

AMD AAI Venice SP7 Delidded

I wanted to just sit and discuss a perspective on the next-generation AMD EPYC “Venice” CPUs in the era of Agentic AI. We have been covering this topic on our Substack and did a big piece on AMD EPYC 9006 Venice last week, but I wanted to apply it to the next generation of AMD EPYC CPUs because I think AMD’s strategy on server CPUs is becoming much more expansive.

A Perspective on AMD EPYC 9006 CPUs and Agentic AI

A few weeks ago in the aforementioned Substack piece, we explored what it even means to be a data center CPU in the era of Agentic AI, because data centers run a lot of processors. We will spare you the details here, but imagine a 500W CPU with triple-digit core counts, huge amounts of PCIe and memory attached, and then a sub-6W dual-quad-core low-performance Arm processor with maybe 2GB or 4GB of memory attached, and you can argue many processors are in the data center. We have been highlighting this on STH for years, but the ASPEED BMC in most servers runs its own firmware, has its own memory, storage, and network connectivity, runs its own web server and APIs, and so forth, and sits inside a server. If you say that is a data center CPU, then does the same processor sitting in a rear door heat exchanger monitoring temps, pumps, and flow also count as a data center CPU? What about the one sitting in a power shelf? The list goes on, but we had to find a more relevant population, and this is what we came up with.

Axautik Group data center CPU test 2026-Q3

From there, we identified the types of nodes commonly found in those locations. We got some feedback on the Substack framework, so here is a bit more expanded view for folks to consider:

Axautik Group Server CPU Mapping Framework 2026-Q3

Since this is such a large topic these days, I wanted to put together a perspective on Venice mapped to some of these. People who sell CPUs often say that their chips are the best for “everything”, but usually that “everything” is within certain swimlanes. AMD’s own product lineup mirrors this since we have so many versions of the EPYC 9006 family.

First, we have the AMD EPYC SP7. In previous generations, this was the flagship or “high-end” configuration. Now, it is one of many that can be considered a flagship. Key stats are that you can get up to 256 cores and 512 threads (in a 600W part) or up to 96 cores and 192 threads at up to 5GHz (in a 500W part). While there is a 64-core 300W part, five of the nine public SKUs are 500W, and two more are 600W. The 1.6TB/s of memory bandwidth looks like 16 channels of 12800MT/s MRDIMMs.

AMD AAI EPYC 9006 SP7

The other side of Venice is the SP8 socket version that scales from 130W to 400W and from 8 to 128 cores.

AMD AAI EPYC 9006 SP8

At this point, if we are mapping to Intel Xeon, you can think of this like how there are the Intel Xeon 6700P and Xeon 6900P series, just with newer cores, newer memory standards, PCIe standards, and so forth. I am not sure how a 288-core Xeon 6900E series fares when there is an option in the market for a 256-core/512-thread version with much more memory bandwidth and I/O. I bring up that Intel Xeon 6 comparison because Intel’s product planning saw the need to bifurcate the market into a higher-end socket and a lower-end socket years in advance. AMD is now taking a similar approach.

I think this is a critical point, especially when everyone wants an agentic AI CPU. Part of the workload is in the AI Factory, but much of the load will also fall on other data centers. Having a big socket to chase maximum performance and density, and then a smaller socket to fit more traditional racks, seems like the way to go.

Then there is the chip that should make folks excited. With 1.1GB of L3 cache or 12MB L3 cache/ core, plus the 1.6TB/s of memory bandwidth and higher frequencies, the EPYC 9006X is also a SP7 CPU but is designed for more HPC applications. It succeeds the 2022 AMD Milan-X and 2023 AMD Genoa-X, with more modern cores and newer everything else.

AMD AAI EPYC 9006X SP7 Venice X

The interesting thing is that the EPYC 9006X will come out a bit later, but it should be a monster. Let us put it another way, there are many in the industry that look at Meta Muse and its 2 vCPU environments (one core with SMT=2 on) as meaning that the goal is stuffing as many vCPUs into a socket. Others believe the right form is sub-100 cores per socket, maximizing memory bandwidth and per-core performance. The EPYC 9006X is what that second camp would want in an ideal world.

Then there is the AI host processor, the AMD EPYC 9006 LP, which brings LPDDR5X to the AMD EPYC line. To us, this feels like a direct competitor to an NVIDIA Grace or Vera CPU designed to go into a Helios Rack.

AMD AAI EPYC 9006 LP Verano

We have seen a number of 8x GPU AMD Instinct servers with the 192-core Turin Dense parts over the past year or so. Other systems we have tested have had 64-core or 128-core Turin parts. It seems like the answer for these rack-scale designs is hitting a power envelope at the expense of having the most cores in the racks. Technically, this is a Verano, not a Venice CPU, so we changed the title of this piece from EPYC 9006 from Venice to make it easier to slot the series into the data center CPU framework.

With that overview, it is time to map. We have a number of EPYC 9006 series processors and a chart, so now it is time to map.