AI Agent 根据 219 词规格书在 12 小时内设计出完整 RISC-V CPU

AI 芯片设计初创公司 Verkor.io 在今年 3 月发表的一篇研究论文中宣称，其 Agent 式 AI 系统 Design Conductor 自主生成了一颗完整的 RISC-V CPU 核。该系统接收一份仅 219 个单词的需求文档后，在 12 小时内生成了经过验证、可用于版图实现的设计；相较于商用芯片设计通常需要 18 至 36 个月的周期，这一速度快了多个数量级。

[图片来源：Microsoft]

Verkor 表示，这是自主 Agent 首次从规格书一直完成到可工作的 CPU 以及 GDSII 版图文件。最终得到的处理器 VerCore 是一款五级流水线、顺序执行、单发射核心；其在 ASAP7 7nm 工艺设计套件上实现了 1.48 GHz 的时序，并在 CoreMark 基准测试中取得 3,261 分。

Verkor 的论文详细介绍了该处理器的流水线架构，其中包括取指、译码、执行、访存和写回阶段，并具备提前分支判定与操作数前递功能。

在优化过程中，该系统还独立实现了一个高速 Booth-Wallace 乘法器，频率达到 2.57 GHz；同时，Agent 在实现并测试了一周期和两周期两种方案后，选择了分支预测错误代价为一个周期的设计。Verkor 将 VerCore 的 CoreMark 性能与 Intel 于 2011 年推出、采用 Penryn 架构的移动芯片 Celeron SU2300 进行了比较。

按照行业标准，一颗没有缓存、没有乱序执行能力的五级顺序执行核心属于相对直接的设计。Verkor 自己的论文也指出，前沿芯片的开发成本超过 4 亿美元，需要数百人的工程团队投入 18 至 36 个月；而 VerCore 比这些设计简单得多。尽管如此，即使在这一相对较低的复杂度水平下仍需要“数百亿级 Token”，但从规格到版图的完整自主运行仅耗时 12 小时，依然值得关注。

[图片来源：Verkor.io]

VerCore 尚未完成实体流片，而是使用 RISC-V ISA 参考模拟器 Spike 进行仿真验证。ASAP7 也是学术工艺设计套件，而非可量产的 7nm 工艺节点。Verkor 表示，该核心能够在仿真中运行一个 uCLinux 变体。

Verkor 的论文坦率说明了底层语言模型的局限性，并承认 Agent 有时会“低估解决某些问题所需工作的复杂程度”。例如，在一次未能满足时序要求的情况下，Design Conductor 试图通过大幅改动来“加深流水线”，而不是先寻找更简单的原因。

另一个案例中，研究人员观察到，该模型会像理解顺序代码一样推理 Verilog——一种事件驱动语言。研究人员解释称：“尽管我们发现这并未影响 DC 实现功能正确性的能力，但它使 DC 调试时序问题变得更具挑战。”

研究人员预计，仍需要 5 至 10 名人类专家引导该系统，才能将其推进至可量产芯片的水平。此外，随着设计复杂度提升，算力需求会以非线性方式增长，这使得整个流程在商业规模上的实用性下降。Verkor 表示，计划在 4 月底前发布 VerCore 的 RTL 源代码和构建脚本；该公司还计划在 DAC（年度电子设计自动化会议）上展示其 FPGA 实现。

此前的 AI 芯片设计工作，例如中国研究人员在 2023 年用不足 5 小时生成一颗 RISC-V CPU，以及较新的 QiMeng 项目，采用了不同的方法论和架构。Verkor 的 Design Conductor 可自主处理从规格到 GDSII 的完整设计流程，但它也面临其他所有 AI 设计芯片共同的限制：尚未获得实体硅片验证。

AI chip design startup Verkor.io claims, in a research paper published in March, that its agentic AI system, Design Conductor, autonomously produced a complete RISC-V CPU core — taking a 219-word requirements document and generating a verified, layout-ready design in 12 hours, which is orders of magnitude faster than the standard 18- to 36-month timelines seen in commercial chip design.

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(Image credit: Microsoft)

This is the first time an autonomous agent has built a working CPU from spec to GDSII layout file, according to Verkor. The resulting processor — VerCore — is a five-stage pipelined, in-order, single-issue core that met timing at 1.48 GHz on the ASAP7 7nm process design kit, scoring 3,261 on the CoreMark benchmark.

Verkor’s paper goes into detail on the pipeline architecture, which includes instruction fetch, decode, execute, memory, and writeback stages with early branch resolution and operand forwarding.

During optimization, the system independently implemented a fast Booth-Wallace multiplier that clocked at 2.57 GHz and a one-cycle branch penalty design that the agent selected after implementing and testing both one-cycle and two-cycle variants. Verkor compares VerCore's CoreMark performance to Intel's Celeron SU2300, a 2011 mobile chip based on the Penryn architecture.

A five-stage in-order core with no caches and no out-of-order execution is a fairly straightforward design by industry standards. Verkor's own paper notes that leading-edge chips cost north of $400 million and take 18 to 36 months with engineering teams in the hundreds, but VerCore is far simpler than those designs. That said, the 12-hour timeline is still notable for a fully autonomous run from spec to layout, even if it did require "many tens of billions of tokens" at this comparatively pale level of complexity.

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(Image credit: Verkor.io)

VerCore hasn’t been physically fabricated and was instead verified in simulation using Spike, a reference RISC-V ISA simulator, and ASAP7 is an academic process design kit, not a production 7nm node. Verkor says it can run a uCLinux variant in simulation.

Verkor's paper is candid about the limitations of the underlying language models, admitting that the agent sometimes “underestimates the complexity of work that is required to address certain issues.” For example, in one case, when failing to meet timing, Design Conductor tried to make major changes to "deepen the pipeline, instead of looking for simpler explanations."

In another case, the researchers observed the model reasoning about Verilog, an event-driven language, as if it were sequential code. "While we found that this did not impact DC's ability to achieve functional correctness, it made it more challenging for DC to debug timing issues," the researchers explained.

The researchers estimate that five to 10 human experts will still be required to guide the system toward a production-ready chip. In addition, compute requirements grow non-linearly as design complexity increases, which makes the whole process less practical on a commercial scale. Verkor said it plans to release VerCore's RTL source and build scripts by the end of April, and the company also intends to showcase an FPGA implementation at DAC (the annual Electronic Design Automation Conference).

Previous AI chip design efforts, such as the Chinese researchers who produced a RISC-V CPU in under five hours in 2023 and the more recent QiMeng project, used different methodologies and architectures. Verkor’s Design Conductor handles the full design process from spec to GDSII autonomously, though it shares the same limitation that all other AI-designed chips have: no physical silicon.

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