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统一边缘 AI：Coral NPU 开源标准如何打通从模型到芯片的高能效与可移植智能

英文标题：Unifying Edge AI: How Coral NPU’s open standard brings portable, energy-viable intelligence from model to silicon

Google Research 正式完成 32 位开源 Coral NPU RISC-V 架构设计，发布了关键组件“矩阵执行单元”（MEU），在低于 10 mW 的平均功耗预算下可提供最高 1 TOPS 算力。同步推出的还有 v1.0 开源 IREE/MLIR 编译器工具链，支持将 JAX、PyTorch、TensorFlow 等主流模型通过统一中间表示直接映射到硬件指令，并提供完整开源 RTL。通过与芯原（VeriSilicon）、格罗方德（GlobalFoundries）及新思（Synaptics）的生态合作，Coral NPU 正式进入商用芯片与开发板阶段，助力开发者摆脱边缘硬件碎片化困境，实现“一次模型优化，多端无缝部署”。
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中文

许多极具吸引力的 AI 应用场景正直接发生在我们身边的边缘设备上。首先体现在需要实时理解上下文的可穿戴个人设备中，同时也越来越多地出现在自主机器人和智能传感器等企业级与工业系统中。这些体验要求低延迟、严格的隐私保护以及全天候的高可靠性，无法单纯依赖与云端的持续通信往返。

边缘 AI 与云端形成互补，共同带来最出色的 AI 体验。这依赖于在两者之间持续流动的上下文和智能信息，以“模型级联”（Model Cascade）的模式运行——在合适的时间、合适的地点捕获并处理信息。边缘端的超低功耗模型能够以极低功耗持续感知并实时响应，而在需要更深层次推理时，无缝移交给设备端的大模型或云端模型。

然而，面向边缘端构建应用的难度远超应有水平。云端基础设施已经汇聚在少数几个标准软件栈周围，但边缘领域却被数以百计的专有芯片架构和互不兼容的工具链所割裂。对于机器学习开发者而言，这带来了沉重的“碎片化税”：面对所要部署的每一款目标芯片，你都不得不重写内核算子、重新量化模型，并反复调试芯片厂商特有的私有编译器。

去年，Google Research 推出 Coral NPU 时提出了一个简洁的理念：开放的软硬件标准是统一边缘端、释放开发者生产力与跨平台移植性的唯一途径。 我们基于开放标准打造了 ML-first 的 RISC-V 架构，并搭配可靠的开源工具链，让开发者确信其模型一定能够顺利编译运行，从而使团队能够做到“一次模型优化，跨不同 SoC 厂商、不同设备及不同功耗预算直接部署”。

今天，我们在 Coral 项目上迎来了三大关键里程碑：

软硬件协同设计：在合适的功耗预算下提供合适的性能

解决边缘端的碎片化问题，绝非单纯发布一套指令集那么简单。回顾历史，许多边缘加速器在设计时往往只追求规格表上的高浮点峰值算力，而把软件适配的难题留给编译器团队。在实际应用中，未获支持的神经网络算子层往往会回退（Fallback）到通用 CPU 执行，这不仅会严重拖慢延迟，还会急剧消耗电池电量。

我们从一开始就同步协同设计 Coral NPU 架构及其编译器。我们的重点不是追逐峰值纸面参数，而是追求符合能效实际的计算（Energy-viable compute）：帮助你在具体的应用功耗预算内，交付刚刚好的合适性能。

完成 32 位 Coral NPU 架构

在过去的一年里，我们发布了前三个里程碑的 32 位 Coral NPU 设计：用于控制流的 C 语言可编程 RISC-V 标量前端（Milestone 1）、用于 SIMD 运算的 RVV v1.0 向量协处理器（Milestone 2），以及具备浮点支持的紧耦合内存子系统（Milestone 3）。随着本月矩阵执行单元（Matrix Execution Unit，Milestone 4）的发布，32 位架构已正式拼上了最后一块拼图。

标量与向量单元非常适合处理常规控制逻辑和信号处理，但现代机器学习工作负载——从视觉编码器到 Transformer 的注意力机制层——大部分时间都消耗在 2D 矩阵-矩阵乘法（GEMM）和矩阵-向量乘法（GEMV）上。在 1D 向量引擎上运行 2D 矩阵运算，会迫使芯片不断从内存中反复读取权重和激活值，这往往意味着搬运数据所消耗的能量比实际进行数学计算还要多。

我们的矩阵执行单元利用 RISC-V VME 规范（正式隶属于 Zvt 扩展家族）解决了这一需求，并采用了专用外积乘加（MAC）引擎。由于外积引擎在一个时钟周期内就能计算出完整的 2D 分块运算（每周期 256 次 MAC），它直接在本地寄存器内部复用权重和激活值。这为核心带来了二次方的吞吐量扩展能力，可配置实现最高达 1 TOPS 的算力。

在 sub-10 mW 的功耗预算下配备专用矩阵引擎，彻底改变了开发者在小型电池供电设备上的构建空间。设备不再局限于简单的关键词唤醒或基础动作检测，而是能够连续运行多模态工作负载，包括类似 Gemma 的轻量 Transformer 模型、可穿戴设备上的实时语音翻译、智能耳机上的空间音频过滤，以及机器人上的低延迟视觉感知。

为了帮助芯片团队直接将此开源设计投入商业量产，完整的 32 位 RTL 现已在 GitHub 上开源提供。

通过 v1.0 IREE/MLIR 编译器连接模型与芯片

为了使硬件无需编写自定义汇编即可轻松适配，我们同步发布了 开源 MLIR/IREE 编译器工具链 的 v1.0 基础版本。

借助该软件栈，你可以将来自 JAX、PyTorch 或 TensorFlow 的模型通过 StableHLO 和 TOSA 等标准中间表示导入。编译器会在主机 CPU 与 Coral NPU 核心之间自动划分工作负载，处理算子融合（Operator Fusion），将矩阵分块（Tiling）以适配本地 SRAM 和矩阵累加器，并逐层降级（Progressively lower）直接生成 Coral NPU 标量、RVV v1.0 向量及 VME 矩阵指令。结合我们的开源 MPACT 仿真器和参考 FPGA 设计，软硬件团队甚至在芯片投片制造之前，就能进行模型基准测试和芯片配置调优。

生态系统落地：从晶圆代工与 IP 完备到商业硅片

将开放标准转化为商业芯片，需要整个半导体价值链的深度协同。为了帮助芯片合作伙伴将这一开源设计直接投入商业量产，完整的 32 位 RTL 今日已在 GitHub 上线，我们正与 芯原（VeriSilicon） 合作开展设计实现与设计验证（DV），确保具备直接流片（Turnkey tape-out）能力。我们还与 格罗方德（GlobalFoundries） 在其 12LP+ FinFET 工艺上展开合作——在多次 RTL 迭代中使核心时序加速了 70%，并将标准单元面积缩减了最高 15%，目前正针对矩阵执行单元进行 12LP+ 超低功耗标准库的持续评估。

在商业硅片落地方面，我们与 Synaptics 的合作证明了这一开源标准能够多么迅速地转化为面向不同功耗预算的真实硬件，同时无需割裂软件开发体验。

在 Synaptics 科技日（2026 年 10 月 20 日）上，Synaptics 推出了基于 Coral NPU 技术并由开源 IREE/MLIR 工具链支持的三款 商用芯片 与 硬件产品：

  • 第二代芯片 —— Synaptics Astra SR200 系列：已完成流片并于本月发布，SR200 系列集成了第二代 Coral NPU IP（包括 Milestone 2 RISC-V 向量核心支持），在超低功耗 MCU 封装中提供 400 GOPS 算力，专为电池供电的可穿戴设备和工业传感器节点打造。
  • 全新 Synaptics Coralboard SR 正式亮相：搭载 Astra SR200 系列的全新 Coralboard SR 开发者套件，旨在为 MCU 级别的边缘与具身智能（Physical AI）应用提供快速原型开发支持。
  • Synaptics Coralboard SL 全面上市（GA）：继 Google I/O 上的限量预览后，Coralboard SL 现已通过 DigiKey 面向全球发售，相关 SDK 和文档可在 Synaptics Coralboard 开发者页面 获取。该板卡由配备 1 TOPS Torq™ / Coral NPU 子系统的 Astra SL2619 处理器驱动，可为基于 Linux 的物联网与机器人系统带来 Transformer 和多路视频流视觉加速支持。

由于这两个产品系列都基于相同的架构和编译器底座构建，机器学习团队只需一次模型优化，便可使用同一套工作流将其部署到毫瓦级的可穿戴设备（Coralboard SR）或 1 TOPS 的边缘板卡（Coralboard SL）上。该系列开发板由硬件及核心板（SoM）合作伙伴 Grinn 联合开发，为团队提供了从开发板原型验证到商业量产硬件的平滑路径。

开启 Coral NPU 开发

随着 32 位架构与 v1.0 编译器栈的正式就绪，我们已在着手推进路线图的下一阶段，包括 64 位 Coral NPU 架构以及用于增强安全性的 CHERI 架构支持。

无论你是在设计定制边缘 SoC、开发机器学习编译器，还是准备将模型部署至可穿戴设备与机器人，Coral NPU 都能为你提供一条从模型直达芯片的开放路径。欢迎在此开启你的探索：

English / 原文

Some of the most compelling use cases for AI are happening directly on the devices around us. You see it first in personal devices like wearables that need to understand context in real time, and increasingly in enterprise and industrial systems like autonomous robots and smart sensors. These experiences require low latency, strict privacy, and all-day reliability that cannot depend on a constant round-trip to the cloud.

Edge AI complements the cloud to bring the best AI experiences. These rely on a continuous flow of context and intelligence across both, working as a model cascade where information is captured and processed in the right place at the right time. Ultra-low-power models on the edge can continuously sense and respond in real time, while seamlessly handing off to larger on-device or cloud models when deeper reasoning is needed.

Still, building for the edge is much harder than it should be. While cloud infrastructure has converged around a few standard software stacks, the edge is split across hundreds of proprietary chip architectures and incompatible toolchains. For ML developers, this creates a heavy fragmentation tax, where you end up rewriting kernels, re-quantizing models, and debugging vendor-specific compilers for every chip you target.

Last year, Google Research introduced Coral NPU with a simple idea: an open hardware and software standard is the only way to unify the edge and unlock developer productivity and portability. Our standards based, ML-first RISC-V architecture paired with a reliable open-source toolchain gives developers confidence that their models will compile and run, letting teams optimize a model once and deploy it across different SoC vendors, devices, and power envelopes.

Today, we are reaching three major milestones in the Coral effort:

Co-designing silicon and software: The right performance at the right power envelope

Fixing fragmentation at the edge takes more than publishing an instruction set. Historically, many edge accelerators were designed to hit high peak-compute numbers on spec sheets, leaving compiler teams to figure out software support later. In practice, unsupported neural network layers fall back to a general-purpose CPU, which can hurt latency and drain the battery.

We designed the Coral NPU architecture and its compiler together from the start. Instead of chasing peak metrics, our focus is on energy-viable compute: helping to deliver the right performance at the right power envelope for your application.

Completing the Coral NPU 32-bit architecture

Over the past year, we released the first three milestones of the 32-bit Coral NPU design: a C-programmable RISC-V scalar frontend for control flow (Milestone 1), an RVV v1.0 vector co-processor for SIMD operations (Milestone 2), and a tightly coupled memory subsystem with floating point support (Milestone 3). With this month's release of the Matrix Execution Unit (Milestone 4), the 32-bit architecture is complete.

Scalar and vector units are great for general control logic and signal processing, but modern ML workloads—from vision encoders to transformer attention layers—spend most of their time on 2D matrix-matrix (GEMM) and matrix-vector (GEMV) multiplication. Running 2D matrix math on a 1D vector engine forces the chip to repeatedly load weights and activations from memory, which can mean spending more energy moving data than doing math.

Our Matrix Execution Unit leverages the RISC-V VME specification (formally part of the Zvt family) to address this need and uses a dedicated outer-product multiply-accumulate (MAC) engine. Because an outer-product engine computes a full 2D tile of operations in a single cycle (256 MACs per cycle), it reuses weights and activations directly inside local registers. This brings quadratic throughput scaling to the core, configurable for up to 1 TOPS.

Having a dedicated matrix engine in a sub-10 mW envelope changes what developers can build on a small battery. Rather than stopping at simple keyword spotting or basic motion detection, devices can run continuous, multimodal workloads, including compact transformer models like Gemma, real-time voice translation on wearables, spatial audio filtering on hearables, and low-latency visual perception on robots.

To help silicon teams bring this open design straight into commercial production, the complete 32-bit RTL is available today on GitHub.

Bridging models to silicon with the v1.0 IREE/MLIR compiler

To make the hardware easy to target without writing custom assembly, we are also releasing the v1.0 foundation of our open-source MLIR/IREE compiler toolchain.

With this stack, you can bring models from JAX, PyTorch, or TensorFlow through standard representations like StableHLO and TOSA. The compiler partitions workloads between the host CPU and the Coral NPU core, handles operator fusion, tiles matrices to fit local SRAM and matrix accumulators, and progressively lowers workloads directly to Coral NPU scalar, RVV v1.0 vector, and VME matrix instructions. Alongside our open-source MPACT simulator and reference FPGA design, hardware and software teams can benchmark models and tune silicon configurations before a chip ever goes to fabrication.

The ecosystem in action: From foundry and IP readiness to commercial silicon

Turning an open standard into commercial silicon takes collaboration across the entire semiconductor value chain. To help silicon partners bring this open design straight into commercial production, the complete 32-bit RTL is available today on GitHub, and we are partnering with VeriSilicon on the design implementation and verification (DV) to ensure turnkey readiness for silicon tape-outs. We are also working with GlobalFoundries on their 12LP+ FinFET process - accelerating core timing by 70%, and reducing standard-cell area by up to 15% across RTL iterations, with ongoing evaluation of 12LP+ ultra low-power libraries for the Matrix Execution Unit.

On the commercial silicon side, our collaboration with Synaptics shows how quickly this open standard translates into real hardware across very different power budgets without splitting the software experience.

At Synaptics Tech Day (October 20, 2026), Synaptics is launching three commercial silicon and hardware products built on Coral NPU technology and supported by the open IREE/MLIR toolchain:

  • 2nd-Gen Silicon — Synaptics Astra SR200 Series : Taped out and launching this month, the SR200 series integrates second-generation Coral NPU IP (including Milestone 2 RISC-V Vector Core support) to deliver 400 GOPS in an ultra-low-power MCU package. It is built for battery-powered wearables and industrial sensor nodes.
  • New Synaptics Coralboard SR Unveiled: A new Coralboard SR developer kit powered by the Astra SR200 series, designed for rapid prototyping of MCU-class Edge and Physical AI applications.
  • Synaptics Coralboard SL Reaches General Availability (GA): Following our limited-edition preview at Google I/O, the Coralboard SL is now generally available worldwide through DigiKey, with SDKs and documentation on the Synaptics Coralboard Developer page. Powered by the Astra SL2619 processor with a 1 TOPS Torq™ / Coral NPU subsystem, it brings transformer and multi-stream vision acceleration to Linux-based IoT and robotics.

Because both product families build on the same architecture and compiler foundation, ML teams can optimize a model once and deploy it to a milliwatt-class wearable (Coralboard SR) or a 1 TOPS board (Coralboard SL) using the same workflow. Developed in collaboration with hardware and System-on-Module partner Grinn, the Coralboard lineup also gives teams a direct path from devkit prototyping to commercial production hardware.

Start building with Coral NPU

With our 32-bit architecture and v1.0 compiler stack in place, we are already working on the next phase of the roadmap, including a 64-bit Coral NPU architecture and CHERI support for security.

Whether you are designing a custom edge SoC, working on ML compilers, or deploying models to wearables and robotics, Coral NPU can help give you an open path from model to silicon. Here is where you can get started: