Nvidia 以 AI Agent 加速芯片工程
英文标题：🔶 Nvidia Accelerates Chip Engineering with AI Agents
Nvidia 表示，到 2030 年半导体行业预计将生产 2 万亿颗芯片、每月处理约 4100 万片晶圆，芯片与系统复杂度正使传统设计流程难以为继。该公司正将 AI 和加速计算引入芯片架构、仿真、验证、物理实现及系统优化等完整工程闭环，并扩展 Agent Toolkit、CUDA-X 和 PhysicsNeMo 库。Nvidia 称，其 Vera CV100 CPU 在 Synopsys VCS 和 Cadence Jasper 平台的早期测试中，性能达到 AMD Epyc Torrent 系统的 1.5 倍。Cadence 与 Synopsys 也在推进 Agentic AI：前者称 RTL 验证周期可加快 40 倍，后者称可比其他平台快 50 倍交付已验证 RTL，这将推动 EDA 工具链向自主化工程工作流演进。
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中文
十多年前，Nvidia 将全部重心转向人工智能。此后，该公司持续推出 GPU——如今也推出 CPU——以及其他旨在为 AI 系统提供动力的硬件；同时还通过 CUDA-X 提供大量软件库，并在 Nemotron 体系下推出一系列 AI 模型。这使 Nvidia 在快速扩张的 AI 行业中占据领导地位。AI 已主导企业与 HPC 数据中心的发展，也让该公司变得异常富有。
推动这种财富的一部分原因在于，AI 芯片的硅工程随着每一代产品都变得愈发复杂，市场不仅需要更多芯片，也需要更多功能。这种局面正将行业推向传统方法难以应对的边界。Nvidia 计算工程副总裁兼总经理 Tim Costa 对此的表述，并不只是为了满足需求而扩大规模。
Costa 在一次与记者进行的视频通话中指出，预计到 2030 年，行业将生产 2 万亿颗芯片，并每月处理约 4100 万片晶圆。此外，单个封装正逼近 1 万亿个晶体管，而完整计算系统的晶体管数量也将迈向千万亿级。同时，一颗芯片从开发到上市可能需要数年时间，因为工程师要在仿真、验证和实现环节投入数年。在 AI 加速发展的时代，这几乎是一段漫长的生命周期。
复杂性超越传统芯片设计
“关键不在于某一个数字，而在于规模、架构、封装和系统复杂性之间的相互作用，”他说，“传统设计流程根本无法跟上如此规模的挑战。为了应对它，AI 和加速计算正从生产力工具转变为基础性的工程基础设施。”
这正是 Nvidia 及其他芯片工程公司开始转向 AI 的领域。
“半导体创新端到端耦合的特性，使这种复杂性进一步加剧，”Costa 说，“芯片架构上的决策会影响原子尺度制造、先进封装的功耗与散热，以及整个系统的行为。AI 能帮助工程师探索更多设计备选方案，并在这些相互作用中作出更好的决策。加速计算则让这些决策背后的高保真仿真、验证和优化足够快，从而可以反复执行。”
他解释说，将 AI 引入芯片开发流程并不是要替代物理规律或设计规则，而是让工程师能够把这类检查纳入流程闭环，并更频繁地使用它们。他补充道：“机会在于加速完整的工程闭环，而不是孤立的工具。”
Nvidia 还在扩展其 Agent Toolkit，纳入升级后的 CUDA-X 和 PhysicsNeMo 库，用于训练和部署工程 AI。
此外，这家厂商正与芯片工程公司 Cadence 和 Synopsys 合作，利用其基于 Arm 的“Vera”CV100 CPU（如下所示）加速未来几代 CPU 和 GPU 的开发。
Vera 搭载 88 个由 Nvidia 设计的定制“Olympus”CPU 核心，以及一个带宽达 1.2 TB/秒的 LPDDR5X 内存子系统。Nvidia 表示，该产品采用公司第二代 Scalable Coherency Fabric 网格互连，为工程应用提供强大的单核性能、高内存带宽和低延迟。
“Nvidia 正在将 Vera 部署到用于打造未来 CPU 和 GPU 的 EDA（电子设计自动化）工作流中，包括仿真、形式验证和物理实现，”Costa 表示，并指出早期工程测试显示，Vera 在 Synopsys 的 VCS 和 Cadence 的 Jasper 平台上运行时，性能达到 AMD Epyc Torrent 系统的 1.5 倍。“它的实际价值在于缩短仿真验证运行时间。工程团队可以更快迭代。我们正与 Cadence 和 Synopsys 合作，为 Vera 优化领先的 EVA 应用，让 Vera 参与设计 Rosa。”
“Rosa”当然是 Nvidia 的下一代 CPU，基于其 Rigel 核心构建。该产品计划于 2028 年作为该厂商即将推出的 Feynman 数据中心平台的一部分发布。
Cadence 和 Synopsys 都在大力推进 Agentic AI 的应用，用于其 EDA 及其他芯片设计能力。Cadence 于 2 月发布了用于硅设计和验证的 Agentic 工具 AI Super Agent；在随后的两个月中，又公布了与 Nvidia、TSMC 和 Google 的合作，围绕利用 AI Agent 进行芯片与系统设计展开合作。上个月，该公司推出了 AuraStack AI Super Agent（如下所示），用于自动化芯片设计与验证的前端 Agentic 工作流。
Cadence 表示，在工程师指挥下，这些 AI Super Agent 可以同时执行数百项仿真，在不到一天内完成目前需要五周的工作，从而实现快 40 倍的寄存器传输级（RTL）验证周期。
Synopsys 不仅与 Nvidia 合作，本周还宣布了分别与 AMD、Microsoft 及 Intel 开展的类似 Agentic AI 合作。在本周于加州举办的设计自动化会议上，Synopsys 展示了其全自主设计验证工作流（如下所示）。该工作流基于其 Agentic 平台和 AgentEngineer 技术，整合了 Nvidia 的新 Nemotron 3 Ultra 模型、Agent Toolkit 以及 OpenShell 运行时等技术。该厂商称，它可比其他平台快 50 倍交付已验证的 RTL。
Nvidia 于 3 月推出 Agent Toolkit，其核心组件包括 Nemotron 模型和 OpenShell 运行时；一个月前，该公司又发布 Nemotron 3 Ultra——一款面向芯片设计 Agentic 编程的开放模型。现在，这家厂商正在扩展该工具包，包括重新设计 PhysicsNeMo，使 Agent 能够训练和部署用于设计与仿真工作的 AI 物理模型。
“PhysicsNeMmo 最初是一个框架，帮助专业人员构建、训练和部署用于 AI 物理的 AI 模型，”Costa 说，“我们现在正将这些专业知识组织成一组开放、可组合的库，并为其赋予可供 Agent 使用的技能。这些库覆盖实用层面和工程工作流所需的能力，包括物理感知操作、GPU 原生网格处理、分布式训练和数据整理；其中的技能则对可重复执行的任务进行编码，例如模型加速、配置训练方案、创建数据管道或整理数据集，包括应调用哪些工具、应生成哪些输出，以及应如何检查结果。”
他补充称，“这种转变是从由专家手动操作的框架，转向 Agent 能够在更大工程流程中调用、组合和验证的 AI 物理能力。”
CUDA-X 已通过 cuDSS 提供用于直接稀疏求解器的加速库，面向对 EDA 和科学仿真至关重要的大型复杂稀疏线性系统；还提供了 cuEST，用于达到设备需求规模的量子化学模拟。现在，它还纳入了 cuISS，用于在 GPU 上处理物理和工程仿真的大型稀疏线性系统。
“许多工程应用都始于偏微分方程，”Costa 说，“一旦这些方程被离散化——即转化为可由计算机进行离散计算的形式——工作负载往往会变成一个非常大的稀疏线性系统。直接求解器仍然不可或缺……但许多工程应用为了内存效率和可扩展性，需要迭代方法。cuISS 将 GPU 原生的迭代稀疏求解器和预条件构建模块带入 CUDA-X。”
English / 原文
More than a decade ago, Nvidia turned its full focus on artificial intelligence, and since then has been churning out GPUs – and now CPUs – and other hardware designed to power AI systems as well as a wealth of software libraries through CUDA-X and a family of AI models with under the Nemotron umbrella. This has put Nvidia in a leadership role in a rapidly expanding AI industry that has taken over enterprise and HPC datacenter development and made the company extraordinarily wealthy.
Part of what drives that wealth is the fact that silicon engineering for AI is increasingly complex with every generation, with demand not only for more chips but also more capabilities, a situation that is pushing the industry beyond what traditional methods can handle. Tim Costa, vice president and general manager of computational engineering at Nvidia, put it in terms that go beyond simply scaling to meet demand.
Speaking with journalists in a video call, Costa noted that by 2030 the industry is expected to produce 2 trillion chips and process about 41 million wafers a month. In addition, individual packages are approaching a trillion transistors while entire computing systems are on their way to transistor counts that will reach into the quadrillions. At the same time, bringing a chip to market can take years as engineers spend years on the simulation, verification, and implementation steps. That’s a lifetime in the accelerated age of AI.
Complexity Outpaces Tradition Chip Design
“The key point is not any one number; it's the interaction of scale, architecture, packaging, and system complexity,” he said. “The traditional design process just can't keep pace with that scale of challenge. To meet it, AI and accelerated computing are moving from productivity tools into being foundational engineering infrastructure.”
This is where Nvidia and other chip engineering firms are turning to AI.
“This complexity is compounded by the coupled end-to-end nature of semiconductor innovation,” Costa said. “Decisions in chip architecture affect atomic-scale manufacturing, advanced packaging power, thermals, and the behavior of the complete system. AI helps engineers explore far more design alternatives and make better decisions across those interactions. Accelerated computing makes the high-fidelity simulation, validation, and optimization behind those decisions fast enough to repeat.”
Rather than replacing physics or design rules, bringing AI into the chip development process lets engineers put such checks into the loop and use them more often, he explained, adding “the opportunity is to accelerate the full engineering loop, not isolated tools.”
Nvidia also is expanding its Agent Toolkit to include updated CUDA-X and PhysicsNeMo libraries for training and deploying engineering AI.
In addition, the vendor is working with chip engineering firms Cadence and Synopsys in using its Arm-based “Vera” CV100 CPU (below) to accelerate future generations of its CPUs and GPUs.
Vera holds 88 custom “Olympus” CPU cores designed by Nvidia and a 1.2 TB/sec LPDDR5X memory subsystem. The company’s second-generation Scalable Coherency Fabric mesh interconnect for strong per-core performance, high memory bandwidth, and low latency for engineering applications, according to Nvidia.
“Nvidia is deploying Vera across the EDA [electronic design automation] workflows used to create our future CPUs and GPUs, including simulation, formal verification, and physical implementation,” Costa said, noting that early engineering testing shows Vera running on Synopsys’ VCS and Cadence’s Jasper platforms provide 1.5 times the performance of AMD’s Epyc Torrent systems. “Its practical value is shorter simulation verification runs. Engineering teams can iterate faster. We are working with Cadence and Synopsys to optimize leading EVA applications for Vera by putting Vera to work helping design Rosa.”
“Rosa,” of course, is Nvidia’s next-generation CPU built on its Rigel core. It is due to launch in 2028 as part of the vendor’s upcoming Feynman datacenter platform.
Both Cadence and Synopsys are going hard into using agentic AI for their EDA and other chip design capabilities. Cadence in February announced AI Super Agent, an agentic tool for silicon design and verification, and in the following two months unveiled partnerships with Nvidia, TSMC, and Google around using AI agents for chip and system designs. Last month came the launch of AuraStack AI Super Agent (below) for front-end agentic workflow for automated chip design and verification.
The AI Super Agents, at the direction of engineers, can simultaneously implement hundreds of simulation to do in less than a day work that now requires five weeks, providing 40-times faster Register-Transfer Level (RTL) validation cycles, according to Cadence.
For its part, Synopsys not only is partnering with Nvidia, but this week announced similar agentic AI-based collaborations with AMD, Microsoft, and Intel. At the Design Automation Conference this week in California, Synopsys demonstrated its Fully Autonomous Design Verification Workflow (below) that is based on its agentic platform and AgentEngineer technology and includes Nvidia technologies, such as its new Nemotron 3 Ultra model, Agent Toolkit, and OpenShell runtime. The vendor said it can deliver validated RTL 50 times faster than other platforms.
Nvidia in March launched its Agent Toolkit, with core components including the Nemotron models and OpenShell runtime and a month ago unveiled Nemotron 3 Ultra, an open model for agentic coding for chip designs. Now the vendor is expanding the toolkit, including with a rearchitected PhysicsNeMo so agents can train and deploy AI physics models for design and simulation work.
“PhysicsNeMmo began as a framework that helped specialists build, train, and deploy AI models for AI physics,” Costa said. “We are now organizing that expertise as a collection of open, composable libraries with agent-ready skills. The libraries cover the practical layers and engineering workflow needs, physics-aware operations, GPU-native mesh processing, distributed training, and data curation, the skills that encode repeatable instructions for tasks such as model acceleration, configuring a training recipe, creating a data pipeline, or curating a data set, including which tools to call, what outputs to produce, and how the results should be checked.”
He added that “the shift is from a framework an expert operates manually to AI physics capabilities an agent can invoke, compose, and validate inside a larger engineering process.”
CUDA-X has included acceleration libraries for direct sparse solvers in cuDSS for large and complex sparse linear systems that are key to EDA and scientific simulation, as well as cuEST for quantum chemistry simulations to scales that meet the need of devices. It now includes cuISS for large sparse linear systems for physics and engineering simulations on GPUs.
“Many engineering applications begin with partial differential equations,” Costa said. “Once those equations are discretized – or made discrete-ready to compute on a computer – the workload often becomes a very large sparse linear system. Direct solvers remain essential ... but many applications in engineering require iterative methods for memory efficiency and scalability. cuISS brings GPU-native iterative sparse solvers and preconditioning building blocks into CUDA-X.”