OpenAI 如何利用自家 LLM 设计 AI 芯片

8 月 25 日，OpenAI全面发布了公司首款 AI 加速器芯片 Jalapeño。Jalapeño 可提供最高 13.4 PFLOPS 的 4 位计算性能，并可访问 232 GB 当前最先进的内存，以高达 15.4 TB/s 的速度与其连接。OpenAI 引述的基准测试显示，与该公司目前依赖的 Nvidia GB300 相比，Jalapeño 可将端到端延迟——即从输入提示词到生成最后一个 token 的时间——最多降低 3.6 倍，同时功耗更低。

Jalapeño 在大规模部署到 OpenAI 推理集群后，这些数字能否转化为实际收益仍有待观察；但性能只是故事的一半。另一半在于该芯片的设计方式——正如你或许预料到的，这一过程得到了 OpenAI 大语言模型（LLM）的加速。Jalapeño 从最初架构概念到首批硅片的周期不足 20 个月。首版 RTL——即定义芯片逻辑的寄存器传输级代码——到流片之间仅间隔 9 个月；流片意味着完成的设计被送往制造。

这已经是很快的进度，但专家认为，随着 LLM 性能提升并更深度地整合进芯片设计工具，这一速度可能很快显得并不算快。不出所料，OpenAI 对其中的机会十分看好。OpenAI 硬件副总裁 Richard Ho 表示：“这些模型赋予了我们的工程师超能力。我们的工程师仍在推动工作，他们仍是对一切情况作出最终判断的人。但他们能够快得多地完成事情，也能探索多得多的路径。”

OpenAI 以小型设计团队实现快速成果

Ho 表示，在整个项目过程中，设计 Jalapeño 的团队平均人数不足 100 人；目前团队规模仍大致维持在 100 人，正推进第二代和第三代设计。这一数字涵盖硬件团队内从系统设计到软件及供应链的广泛岗位，但不包括该项目合作方 Broadcom 的人员。

OpenAI 与 Broadcom 之间的分工大体上是设计与实现的划分。OpenAI 团队负责端到端系统设计，包括推理加速器、内存层级和网络。Ho 表示，Broadcom 则负责“从逻辑门开始的物理设计”。

与 Broadcom 的合作也令一些人对 OpenAI 的研发速度持较为保留的看法。智能体芯片设计初创公司 Verkor.io 联合创始人 David Chin 表示，“他们给出的时间表相当可信”，但他认为 Broadcom 的帮助对 Jalapeño 的快速推进至关重要。“如果让其他人从零开始，这不可能做到。”同为 Verkor.io 联合创始人的 Ravi Krishna 称 OpenAI 的速度“是一个相对令人印象深刻的成果”，但补充说，如果项目在今天启动，LLM 能力的进步可能带来更快的时间表。

加州大学圣迭戈分校杰出教授 Andrew Kahng 也认为 OpenAI 的速度值得注意，称其“在当今很可能属于业内最佳水平”。Kahng 回忆起他参与组织的一场 2016 年 IEEE 设计自动化未来研讨会。当时仍在 Google 任职工程师的 Richard Ho 在会上担任主题演讲嘉宾。Ho 对设计自动化有明确看法，并将完成芯片设计所需的时间视为团队一天内能够完成多少次迭代的函数。

OpenAI 的 LLM 如何加速 Jalapeño 设计

马里兰大学半导体计划与创新主任 Ankur Srivastava 表示：“芯片设计中的自动化本身已经存在数十年，这不是一个新问题。”不过，他表示，LLM 与此前自动化工具的不同之处在于，它们能够理解语言和代码。这使其尤其适合那些“仍处于问题语言领域内”的芯片设计任务。

OpenAI 团队设计了一套利用这一优势的工作流。OpenAI 的前端工作流围绕加速硬件综合（XLS）构建；XLS 是一套开源高层次综合工具链，最初由 Google 开发。高层次综合是一种芯片设计自动化形式，使工程师可在更熟悉的编程环境中设计芯片。就 XLS 而言，芯片设计师可使用 DSLX——一种受 Rust 启发的领域专用语言——以及 C++ 等语言编写设计。随后，XLS 会将其转换为 Verilog，后者是一种用于描述电子系统的硬件描述语言。

OpenAI 技术人员 Chris Leary 表示：“我们当时在思考如何利用 AI 加快项目，而 AI 更擅长处理看起来像软件的东西。XLS 在某些方面看起来就像软件，因此得到了这种优势。”Leary 在 Google 任职期间创办了 XLS，因此他也非常熟悉 XLS 应有的工作方式，这同样有所帮助。

Kahng 同意，使用 AI 加速 XLS 等高层次综合是合理的，因为这“对 LLM 来说更自然”，并提供了快速迭代的机会。“我认为这是一种具有普遍实用性的工作流，而且它在未来会持续发展。”

同样的逻辑促使 Jalapeño 团队聚焦于软件优化。今年 5 月，首批芯片从晶圆厂返回后，团队使用内部 AI 模型 为 SemiAnalysis 的 InferenceX 等基准测试设计运行软件。在 DeepSeek 的多头潜在注意力内核基准测试中，性能在大约 40 小时内从理论上限的 0.31%——该上限由芯片的计算和内存带宽决定——提升至 88.94%。Ho 表示，这一结果可以复现，因此可缩短晶圆厂交付首批芯片到量产爬坡之间的时间。“我们所有的进度假设都将建立在我们现在拥有这一能力的事实上。”

Jalapeño 被设计用于部署在包含 2,048 枚芯片的 Pod 中。OpenAI

虽然 Jalapeño 团队 AI 辅助工作流的大体框架是 Ho 和 Leary 预先设想的，但 OpenAI 模型的改进也带来了一些意外惊喜。

Leary 表示，该项目最初获得了 OpenAI o3 等模型的协助；o3 于 2025 年 4 月向公众发布，但 Jalapeño 团队更早便可使用。到项目收尾时，团队已经能够使用 GPT-6 Astra 的前身模型；GPT-6 Astra 直到 2026 年 9 月 3 日才公开发布。Leary 表示，较新的模型无需借助 XLS 从常规编程语言进行转换，便能直接处理 Verilog，并且已接近能够自行操作专有设计工具。

Ho 还确认，团队能够使用面向芯片设计微调、但尚未向公众开放的内部 LLM。不过，他拒绝详细说明所使用的模型；他补充称，Jalapeño 团队与 OpenAI 研究团队开展了合作。尽管用于设计 Jalapeño 的所有具体模型并未公开，Ho 表示，目标是将项目经验带入公司的商业 LLM。“可以肯定地说，Astra 及后续模型将非常擅长芯片设计。”他说。

AI 在后端优化中的作用较小，但这可能改变

如前所述，OpenAI 在 Jalapeño 上的大部分工作集中于芯片设计的“前端”。这一阶段涵盖从最初概念出发、编写定义设计的 RTL 代码，到验证设计在物理实现后是否能够正常工作的任务。大量“后端”设计工作——包括互连布线、完成并验证时钟和电源规格，以及将所需设计信息发送至晶圆厂——则交由 Broadcom 负责，后者推动该芯片完成生产。

但这并不意味着 OpenAI 的工作流忽略了后端。Jalapeño 团队包括物理设计工程师，他们与 Broadcom 的对应团队协作，就芯片的平面规划、布线及其他事项提供指导。

在 IEEE Hot Chips 2026 上，Ho 和 Leary 给出了 AI 引导物理设计优化所带来收益的数据：相较经过优化的人工基线，矩阵乘法单元的面积缩小了 10%。换言之，OpenAI 声称，AI 引导的优化帮助其在相同面积的硅片上设计出比此前更多的电路。

Broadcom 使用了自身的内部工作流。该公司的团队无法使用 OpenAI 用于协助设计 Jalapeño 的内部模型，但能够访问 OpenAI 面向公众的商业模型。

Verkor.io 的 Ravi Krishna 表示，OpenAI 对后端设计的处理方式如今已显得有些保守，并认为这与项目启动的时间有关——该项目始于 2024 年 10 月。“过去四到五个月的模型已经有所改进。从 [2026 年] 4 月开始……它们才真正开始能够更好地处理这些任务。”他说。Verkor.io 联合创始人 Suresh Krishna 也认同这一点，称“没有理由不能构建一个智能体循环，让它大幅加速流程后端”。

Ho 和 Leary 还暗示，相比团队下一阶段的工作，用于设计 Jalapeño 的工作流可能会显得有些老派。

Leary 表示：“如你所想，使用 [Jalapeño] 时，我们试图尽可能快地推进。因此，这里存在一种权衡：‘我们是要花时间进行一些创新，还是要采用我们知道在历史上行之有效的方法？’到了第二代，我们有了一次重置的机会，可以重新审视所有希望搭建起来的事项。”

Ho 表示，第二代芯片的工作流“有很多我们正在引入 [AI] 的地方”。他提到，可在验证和物理设计中更多地使用 AI。Leary 补充说，团队现在已有用于自动处理和查看波形的工具。这些工具可自动分析与故障相关的芯片时钟信号，并可能改善硬件仍处于设计阶段时的调试工作。

尽管预期会有这些改进，Ho 和 Leary 明确表示，他们不认为芯片设计能够完全自动化。Ho 解释道：“我们并不是说，任何人仅仅使用 [OpenAI 的编程平台] Codex，就能来构建最先进、前沿的 AI/ML 加速器芯片。我们是在说一些非常具体的事情，即如何更好地使用 Codex，以及我们如何专注于一支小型团队和快速时间表，以获得高质量成果。”

On 25 August, OpenAI fully unveiled Jalapeño, the company’s debut AI accelerator chip. Jalapeño delivers up to 13.4 petaflops of 4-bit compute and accesses 232 gigabytes of the most advanced memory available, linking to it at a blazing 15.4 terabytes per second. Benchmarks cited by OpenAI show that Jalapeño can reduce end-to-end latency (the time between prompt to last token) by up to 3.6x when compared to Nvidia’s GB300—a chip the company currently relies on—and do so while consuming less power.

Whether these figures translate into real-world gains once Jalapeño enters widespread service in OpenAI’s inference fleet remains to be seen, but performance is only half the story. The other half is how the chip was designed—a process which, as you might expect, was accelerated by OpenAI’s large language models (LLMs). Jalapeño moved from first architecture concept to first silicon in under 20 months. Only nine months separated the first RTL—the register-transfer level code defining the chip’s logic—from tapeout, when the finished design goes to manufacturing.

That’s a rapid timeline, yet experts believe it could soon look slow as LLMs improve and become more deeply integrated into chip design tools. OpenAI, unsurprisingly, is bullish about the opportunities. “The models are giving superpowers to our engineers,” says Richard Ho, vice president of hardware at OpenAI. “Our engineers are still driving the work, they’re still the final arbiter of what’s going on. But they can do things a lot faster, they can explore a lot more paths.”

OpenAI achieved fast results with a small design team

Ho says the group that designed Jalapeño averaged fewer than 100 people over the course of the project and continues to stand at roughly 100 today as the team pursues second and third-generation designs. That number includes a broad swath of roles across the hardware team, from system design to software and supply chain, but not those at Broadcom, which partnered with OpenAI on the project.

The division of labor between OpenAI and Broadcom was generally split between design and implementation. OpenAI’s team was responsible for end-to-end system design including the inference accelerator, the memory hierarchy, and networking. Broadcom handled “physical design from the gates onward,” says Ho.

The partnership with Broadcom dampened some opinions on OpenAI’s speed. David Chin, co-founder at agentic chip design startup Verkor.io, says “the schedule they gave us is quite credible,” but believes that Broadcom’s help was essential to Jalapeño’s rapid timeline. “If you have somebody else start from scratch, it won’t be possible.” Ravi Krishna, also a co-founder at Verkor.io, called OpenAI’s speed “a relatively impressive result,” but added that he expects that improvements in the capabilities of LLMs could result in even quicker timelines if the project started today.

Andrew Kahng, distinguished professor at UC San Diego, also found OpenAI’s speed notable, saying it’s “likely best in class today.” Kahng recalls a 2016 IEEE Design Automation Futures workshop, which he co-organized. The workshop included Richard Ho, at the time an engineer at Google, as a keynote speaker. Ho had strong opinions on design automation and framed the time required to complete a chip’s design as a function of the number of iterations a team could complete in a day.

How OpenAI’s LLMs accelerated Jalapeno’s design

“Automation itself has existed in chip design for many decades. It’s not a new problem,” says Ankur Srivastava, director of semiconductor initiatives and innovation at the University of Maryland. Where LLMs differ from prior automation tools, however, is their ability to understand language and code. He says this makes them particularly suited for chip design tasks that “are still in the linguistic domain of the problem,” he says.

The team at OpenAI designed a workflow that takes advantage of this strength. OpenAI’s front-end workflow was built around Accelerated Hardware Synthesis (XLS), an open-source high-level synthesis chain of tools originally developed at Google. High-level synthesis is a form of chip design automation that allows engineers to design a chip in a more familiar programming environment. In the case of XLS, chip designers can write in languages such as DSLX (a domain-specific language inspired by Rust) and C++. XLS then converts these to Verilog, a hardware description language used to describe electronic systems.

“We were thinking about how to leverage AI to make the project faster, and the AI was much better at software-looking things,” says Chris Leary, member of technical staff at OpenAI. “XLS in some ways looks like software, so it got that benefit.” It helped, too, that Leary was extremely familiar with how XLS should function, as he started it during his time at Google.

Kahng agrees that the decision to use AI to accelerate high-level synthesis, such as XLS, makes sense, as it’s “more natural for the LLM to work with” and provides the opportunity for fast iteration. “I see this as a generally useful workflow, and it’s one that ‘has legs’ going into the future.”

The same logic led the Jalapeño team to focus on software optimization. When the first chips came back from the foundry in May, the team pointed its internal AI models at designing software to run benchmarks such as SemiAnalysis’ InferenceX. On DeepSeek’s multi-head latent attention kernel benchmark, performance climbed from 0.31 percent of the theoretical ceiling (set by the chip’s compute and memory bandwidth) to 88.94 percent in roughly 40 hours. Ho says this result is repeatable, so the time between when foundries deliver the first chips and when production ramps up can be reduced. “All our schedule assumptions are going to be based on the fact we have this capability now.”

Jalapeño is designed for deployment in pods that include 2,048 chips.OpenAI

While the broad strokes of the Jalapeño teams’ AI-assisted workflow were guessed by Ho and Leary up front, improvements in OpenAI’s models did offer a few surprises.

Leary says that the project began with assistance from models like OpenAI’s o3, which was released to the public in April of 2025 (but available to the Jalapeño team earlier). By the time the project had wrapped up, however, the team had access to models that were precursors to GPT-6 Astra, which wasn’t publicly released until 3 September 2026. The newer model can work directly in Verilog without needing XLS’s translation from ordinary programming languages, and it’s close to being able to operate proprietary design tools on its own, says Leary.

Ho also confirmed that the team had access to internal LLMs fine-tuned for chip design that are not available to the public. He declined to detail the models used, however, he added that the Jalapeño team partnered with OpenAI’s research team. While not all specific models used to design Jalapeño are publicly available, the goal is to bring lessons learned from the project into the company’s commercial LLMs, says Ho. “It’s safe to say that Astra and following models will be very good at chip design,” he says.

AI was less useful for backend optimization, but that could change

As mentioned, the bulk of OpenAI’s work on Jalapeño focused on “front end” of chip design, which spans the tasks that take a chip from initial concept, through writing RTL code to define the design, and through verification of the design will work when physically implemented. Much of the “back end” design, which includes tasks like routing interconnects, completing and verifying the clock and power specifications, and sending the required design information to the foundry, was handed off to Broadcom, which carried the chip through production.

That’s not to say OpenAI’s workflow ignored the backend, though. The Jalapeño team includes physical design engineers who work with their counterparts at Broadcom to provide guidance on the chip’s floorplan and routing, among other things.

At IEEE Hot Chips 2026, Ho and Leary put numbers on the gains from AI-guided physical design optimization, including an area reduction of 10 percent for the matrix multiplication units as measured against an optimized human baseline. In other words, OpenAI claims AI-guided optimization helped design more circuits into the same area of silicon than would have been possible before.

Broadcom used its own internal workflow. The company’s team did not have access to the internal models OpenAI used to help design Jalapeño, but it did have access to OpenAI’s public, commercial models.

Verkor.io’s Ravi Krishna says that OpenAI’s approach to backend design already feels a bit conservative, and believes that to be an artifact of when the project (which began in October of 2024) took place. “The models from the last four to five months have improved. From April [2026] onwards… is when they really started to be able to handle those tasks better,” he says. Verkor.io co-founder Suresh Krishna agreed, saying “there’s no reason you couldn’t have an agentic loop that largely accelerates the backend of the process as well.”

Ho and Leary also hinted that the workflow used to design Jalapeño may look old-fashioned compared to the team’s next efforts.

“As you can imagine with [Jalapeño], we were trying to go as fast as we could. So there’s a trade-off between ‘do we want to take time to do some innovation, or do we want to do things that we know work historically?’” says Leary. “With the second generation, we have a kind of reset opportunity to ask about all the things we want to get set up for.”

Ho says the second-generation chip’s workflow has “a lot of places that we are introducing [AI].” He mentions opportunities to do more with AI in verification and physical design. Leary adds that the team now has tools for automatic waveform manipulation and viewing. This automates analysis to identify chip clock signals associated with failures and could improve debugging the hardware while it’s still being designed.

Despite these expected improvements, Ho and Leary were clear that they don’t believe chip design can be fully automated. “We’re not saying that anyone can come and just build state-of-the-art, frontier AI/ML accelerator chips using just [OpenAI’s coding platform] Codex,” explains Ho. “We are saying some very specific things about how to be better at Codex, and how we are focusing on a small team and fast timelines to reach quality results.”

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